This is a national stage application filed under 35 U.S.C. 371 of PCT/JP97/00411 filed Feb. 17, 1997.
The present invention relates to a data processing apparatus such as a microprocessor or a digital signal process (DSP), and more particularly to a technique effectively applicable to instruction buffers.
Along with the development of sophisticated information apparatuses including personal computers (PCs), personal digital assistants (PDAs), digital cellular units and car navigation aids in recent years, the need to reduce power consumption of large scale integrated circuits (LSIs) mounted on these apparatuses has tremendously increased. This is due to the requirements to make the batteries of portable information devices to keep their charged state longer and to suppress the costs of chip packages and cooling systems for desktop information devices. On the other hand, there are now increasingly active trends to incorporate high performance multimedia functions for processing video and audio signals and communication into information apparatuses. Thus the calculation capacity required of LSIs to execute such multimedia processing is ever increasing, and this constitutes one of the main causes of increased power consumption by LSIs.
Data processing apparatuses including microprocessors and digital signal processors (DSPs) are extensively used as LSIs for executing multimedia processing such as mentioned above. Incidentally, when these data processing apparatuses are to execute multimedia processing, generally the processing is very often to execute a loop consisting of a relatively small number of instructions, because most instances of multimedia processing are ones of digital signal processing mainly consisting of product sum calculations, which are accomplished by repeating many times (1) multiplication and (2) the addition of the result of multiplication to the cumulative sum.
In a digital signal processor, in many cases, an instruction to generate an internal state for repeated execution of a series of instructions (repeat instruction) is supported. A repeat instruction the number of the serial instructions to be executed reiteratively immediately after that and the number of times they are to be executed reiteratively. As a result, instructions to be executed many times reiteratively are executed without having to read them out of a memory (ROM, RAM or cache memory) many times. Therefore, high speed and reduced power consumption can be achieved. Examples are described in xe2x80x9cTMS320C30 Third Generation Digital Signal Processor Users Manualxe2x80x9d published by Texas Instruments Japan Ltd. in 1990 (hereinafter referred to as Prior Art 1) and the Gazette of the Japanese Patent Laid-open No. 293124/1992 (hereinafter referred to as Prior Art 2).
Digital signal processors such as those described in Prior Art 1 and Prior Art 2 presuppose, in order to save the power required for memory accessing by reiteratively reading instructions from an instruction buffer in loop processing, the availability of a repeat instruction. Accordingly there is a problem that the control method uses by digital signal processors such as those of Prior Art 1 and Prior Art 2 cannot be applied to a data processing apparatus provided with no repeat instruction.
In microprocessors of the like for general use instead of specializing in digital signal processing, a repeat instruction is not necessarily supported. In order to be provided with a repeat instruction, an instruction buffer or a repeat control circuit has to be introduced into them. Since, moreover, a repeat control circuit needs many items of hardware such as a repeat start address register, a repeat end address register, a repeat count register, a comparator and a down counter, this is based on a way of thinking that increasing the circuitry scale by introducing such a repeat control circuit is not necessarily advantageous to a microprocessor.
Further, in loop processing emerging in an actual processing, not only simple repetitions but also loops of diverse structures emerge. They include loops to which the control method of reading instructions reiteratively out of the aforementioned instruction buffer cannot be applied as a matter of principle. For instance, where a loop has a plurality of routes of which a different one is followed according to the number of repetitions of the loop, the aforementioned instruction buffer, in which only the instruction executed over the first route is stored, is incompatible with the second and subsequent loops. Therefore the microprocessor should be provided with a means to prohibit the application of control to read instructions reiteratively out of the instruction buffer depending on the structure of the loop. However, as the digital signal processors of Prior Art 1 and Prior Art 2 are provided with no such means and, on every occasion of loop processing, control to reiteratively read out instructions out of the instruction buffer is effected, they involve the problem that correct program processing cannot be accomplished when they come across a loop of a structure to which control to reiteratively read out instructions from the instruction buffer cannot be applied.
On the other hand, a technique to increase the speed or program processing by having, during the execution of loop processing, every instruction in the loop stay in a cache memory without fail is described in the Japanese Patent Laid-open No. 333929/1992 (hereinafter referred to as Prior Art 3). According to Prior Art 3, irrespective of whether or not loop processing is being executed, the cache memory operates whenever an instruction is read (unless miscaching is committed). In order to reduce the power spent in loop processing, the capacity of the cache memory itself should be reduced. However, there is the problem that, as the same small capacity memory is accessed even during non-loop processing, the hit ratio drops, making it impossible to increase the speed of program processing.
An object of the present invention is to provide a data processing apparatus provided with a control means which, in spite of the unavailability of a repeat instruction, reduces the power needed for memory accessing by reading instructions from a small scale buffer reiteratively during loop processing.
Another object of the invention is to provide a data processing apparatus provided with a means to opt to apply, or not to apply, control to read reiteratively, from a small scale buffer, instructions to be reiteratively executed during loop processing.
The aforementioned and other objects and novel features of the invention will become apparent from the description in this specification and accompanying drawings.
The following is a brief description of the typical aspects of the invention disclosed in this application.
Thus, a data processing apparatus (100, 700, 900, 1400 or 1600) for executing instructions stored in a first instruction storing means (102, 702, 902, 1402 or 1602) causes, if, as a result of the execution of an instruction to alter the content of a register (125, 742, 931, 932, 1429 or 1629) prior to a series of instructions to be executed reiteratively, the content of the register (125, 742, 931, 932, 1429 or 1629) satisfies a specific condition, a second instruction storing means (104, 704, 904, 1421 or 1621) to hold the series of instructions to be executed reiteratively and causes them to be outputted reiteratively from the second instruction storing means (104, 704, 904, 1421 or 1621) (see FIGS. 1, 5, 7, 11 and 13).
Further, the final one of the series of instructions to be executed reiteratively in the data processing apparatus (100, 700, 1400, 1600) is an instruction to cause branching to the first one of the series of instructions to be effected when a prescribed condition has come to be satisfied.
Further, the instruction to alter the content of the register (125, 1429 or 1629) in the data processing apparatus (100, 700, 1400 or 1600) is an instruction to designate the logical value of a specific bit (124, 1428 or 1628) contained in the register (125, 1429 or 1629) (see FIGS. 1, 11 and 13).
Further, in the data processing apparatus (700), the instruction to alter the content of the register (125, 1429 or 1629) is an instruction to load the number of times the execution of the series of instructions is to be repeated into the register (742) (see FIG. 5).
Further, in the data processing apparatus (100, 700 or 900), the second instruction storing means is a different instruction buffer (104, 704 or 904) from instruction queues to store a plurality of instructions to be read out of the first instruction storing means prior to execution.
Further, in the data processing apparatus (900), the instruction to alter the content of the register (931 or 932) is an instruction to load information to specify the position of the leading one and information to specify the position of the trailing one of the series of instructions to be repeated into the register (931 or 932) (see FIG. 7)
Further, in the data processing apparatus (900), that the number of the instructions to be executed reiteratively, obtained from the information to specify the position of the leading instruction and the information to specify the position of the trailing information, is not greater than a specific value corresponds to the aforementioned specific condition (see FIG. 7).
Further, in the data processing apparatus (1400 or 1600), the second instruction storing means is instruction queues (1421 or 1621) to store a plurality of instructions to be read out of the first instruction storing means prior to execution.
Further, in the data processing apparatus (100, 700, 900), the second instruction storing means (104, 704 or 904) has a memory holding circuit (1030_k_l) whose constituent elements include a first N channel type MOSFET (1103) of which the gate terminal is connected to a first node (WL-k), either one of the source and drain terminals is connected to a second node (BL-l) and the other to a third node (N1101); a second N channel type MOSFET (1104) of which the gate terminal is connected to the first node (WL-k), either one of the source and drain terminals is connected to a fourth node (BLB-l) and the other to a fifth node (N1102); a third N channel type MOSFET (1101) of which the gate terminal is connected to a fifth node (N1102), the drain terminal is connected to the third node (N1101) and the source terminal is connected to a first operating potential point (GND); and a fourth N channel type MOSFET (1102) of which the gate terminal is connected to the third node (N1101), the drain terminal is connected to the fifth node (N1102) and the source terminal is connected to the first operating potential point (GND) (see FIGS. 1, 5, 7, 8 and 9).
Further, in the data processing apparatus (100, 700 or 900), the second instruction storing means (104, 704 or 904) has an amplifying circuit (1040_l) responsive to input signals pairing the second node (BL_l) and the fourth node (BLB_l) (see FIGS. 1, 5, 7 and 8).
Further in a state in which the content of the register (1429 or 1629) does not satisfy the specific condition in the data processing apparatus (1400 or 1600), any instruction read out of the first instruction storing means (1402 or 1602) is temporarily held by the second instruction storing means (1421 or 1621) at most until it is executed once (see FIGS. 11 and 13).
For instance, the data processing apparatus (100), in order to read out an instruction reiteratively from a buffer (104) in executing a loop, has only to insert an instruction to set a specific bit (124, a buffer control flag) immediately before the execution of the bit. Therefore, it can reduce the power consumed for memory accessing by reiteratively reading the instruction out of the small scale buffer (104) when processing the loop without using a repeat instruction.
Further, unless the specific bit (124, the buffer control flag) is set, the buffer (104) is not accessed in the processing of any loop. Therefore, in order to forbid the application of the control to read an instruction out of the buffer (104) reiteratively in executing a loop, it is sufficient merely to refrain from inserting an instruction to set the specific bit (124, the buffer control flag) immediately before the execution of the loop.